In this paper, we present an automated flow for insertion of pipeline stages in FPGA-based streaming applications in order to increase the throughput. The proposed approach involves the utilization of Xilinx’s Automated Pipeline Analysis tool to estimate the number of pipeline stages, while the Rapid-Wright framework incorporate these stages into a synthesized design. The Vivado Design Suite is then used to place and route the modified netlist. Furthermore, a recycling approach has also been proposed to reduce excess registers. The results show a significant improvement in the maximum operating frequency for designs without any sequential loops (~51%) with a moderate resource overhead, while slight gains (~12%) were also observed for designs containing feedback loops.

The utilization of the used FPGA resources in time is rather low compared to an ASIC due to the lower clock frequency. The efficiency of FPGA resources (lookup tables) can be increased by using designs with many pipeline stages combined with a very high clock frequency. In this work, the automatic insertion of pipeline stages in data paths after synthesis and the usage of high clock frequencies should be investigated. The overall goal is to increase the efficiency and performance of FPGAs. The data paths of critical parts of a design should be analyzed and additional pipeline stages should be automatic inserted.